A semiconductor memory comprises a row-wise and column-wise arrangement of memory cells each having a transistor structure. In the case of charge trapping memory cells, the gate dielectric is formed as a storage layer sequence made from three successive insulation layers, the central one of which is suitable for trapping charge carriers from the channel region, for example hot electrons in the channel (CHE, channel hot electrons) or electrons which pass from the channel into the storage layer by Fowler-Nordheim tunneling. This storage layer sequence may be for example a three-layered sequence of an oxide layer, a nitride layer and a further oxide layer, of which the oxide layers represent the boundary layers of the actual storage layer made of nitride. A charge trapping memory cell is erased, depending on the conception, for example by injection of hot holes or Fowler-Nordheim tunneling.
In the case of a common source architecture, source lines which interconnect the source regions column-wise are present in the semiconductor body. Running parallel thereto are the word lines, which connect the gate electrodes to one another column-wise and are used for the selection of a relevant memory cell. The bit lines run transversely with respect to the word lines and the source lines on the top side and are contact-connected to the drain regions of a respective row. Since, in this case, only the source lines and the source/drain regions are formed as doped regions in the semiconductor material, it is possible for the individual memory cells to be electrically insulated from one another by insulation regions arranged in between. Therefore, an electrical insulation of the cells among one another should also be possible if only the source/drain regions are arranged in the semiconductor material, but no lines are present there. This is the case with a virtual ground architecture, in which the source regions and the drain regions are in each case contact-connected on the top side via bit lines and are selected for the programming and read-out of, in each case, two of said bit lines which are adjacent to one another. However, the problem of a suitable arrangement of said bit lines for the top-side contact-connection of the source/drain regions arises in this case.